The present invention relates to integrated circuit design and, more particularly, to a method, a system and a computer program product for performing a static timing analysis (STA) of an integrated circuit using a hierarchical approach.
In integrated circuit design, static timing analysis (STA) is used to predict the performance of an integrated circuit and to verify that the integrated circuit will function correctly. Specifically, STA is used to predict the arrival times of clock and data signals and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as designed, will function properly with a sufficiently high probability. As integrated circuit designs become more and more complex, performing STA on the full top-level design (also referred to herein as the full design) of an integrated circuit is no longer a viable option due to the large runtime and memory requirements for completing the analysis. Therefore, integrated circuit designers have turned to a hierarchical approach for performing a STA.
With a hierarchical approach, STA is performed on hierarchical entities (i.e., individual blocks of logic, also referred to herein as lower-level entities or macros) that can form any number of hierarchical levels within the full top-level design. Based on the results of the STA at the lower levels of hierarchy, the hierarchical entities are abstracted (i.e., timing abstractions are generated for the hierarchical entities) and these timing abstractions are subsequently used to analyze an overall timing model for the full top-level design. In the hierarchical approach described above, each timing abstraction for each specific hierarchical entity only contains relevant timing information required for incorporating that specific hierarchical entity into the full top-level design or into a block at the higher level of hierarchy. That is, each timing abstraction for each specific hierarchical entity only contains periphery timing information that will impact adjacent hierarchical entities within the design (i.e., that will impact other hierarchical entities that interface with the specific hierarchical entity in the design) and does not include internal timing information. The runtime and memory requirements can be further reduced by allowing a single out-of-context (OOC) timing run to generate a timing abstract that can replace potentially numerous instances of the given hierarchical entity at the next level of hierarchy.
While the overall runtime and memory requirements are reduced with the hierarchical approach, the overall accuracy is also reduced. Specifically, in order to generate an accurate timing abstract for a specific hierarchical entity, some knowledge of timing constraints at the boundary of that specific hierarchical entity (i.e., some knowledge of in-context boundary timing constraints) is required. These in-context boundary timing constraints can include, for example, the arrival times (ATs) of primary inputs (PIs) to the specific hierarchical entity and the required arrival times (RATs) specifying the expected signal arrival time at the primary outputs (POs) of the specific hierarchical entity. Since such boundary timing constraints necessarily impact any timing analysis of the specific hierarchical entity and since boundary timing constraints will vary for different instances of the specific hierarchical entity at different locations within the full top-level design, assumptions must be made about the boundary timing constraints to ensure that the analysis and resulting timing abstraction for the specific hierarchical entity is valid for any possible context (i.e., for any instance of the specific hierarchical entity anywhere in the integrated circuit). In addition, as top-level logic changes are made to address functional or performance issues, the boundary timing constraints of any hierarchical entity (whether used multiple times at the chip level or not) can be impacted. To avoid significant impact, the boundary timing constraints used in an OOC timing run are generally assumed to be overly pessimistic. As a result, timing fails for instances of the specific hierarchical entity are often reported based on conditions that would not occur in any actual context. Consequently, hierarchical entities, which would in fact function properly within the full top-level design, must be redesigned, thereby impacting over-all circuit performance and time-to-market. Therefore, there is a need in the art for an improved technique for performing a static timing analysis (STA) of an integrated circuit using a hierarchical approach, wherein the assumptions made regarding boundary timing constraints during an out-of-context STA of the hierarchical entity are less pessimistic, but still valid for any possible context.